1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems incorporating a register data store from within which access is made using registers.
2. Description of the Prior Art
It is known to provide data processing systems, such as ARM processor cores designed by ARM Limited, Cambridge, England, which have a register bank containing a predetermined number of fixed size registers, such as sixteen registers, each being 32 bits in length. A data value stored within such a register may be read from the register by an appropriate read instruction. The instruction writing to that register and the instruction reading from that register will specify the particular register concerned in the same way, e.g. use the same register number/name.
With the increasing demands for data processing systems capable of performing processing operations upon large volumes of data, such as during moving image data processing etc, there have been developed processing techniques generally referred to SIMD (single instruction multiple data). With these techniques a register containing multiple discrete data elements, such as pixel component values, is subject to a processing instruction applied to all of the data elements within that register in parallel. As an example, it may be desired to multiply the component values of a pixel by a certain scaling factor and the SIMD instruction can control this to take place in response to a single instruction which separately applies the scaling value to each of the different data elements. It will be appreciated that in these systems the data elements are isolated from one another in the sense that the processing performed upon them is not permitted to inappropriately influence other data elements held within the same register.
Whilst SIMD processing techniques do allow the execution in parallel of multiple desired operations, they suffer from the considerable disadvantage that it is generally necessary to spend time and processing cycles arranging the data elements into the necessary positions within the SIMD registers before the SIMD instructions can be executed upon them. This requirement disadvantageously reduces the benefits achieved by SIMD operation.
It is also known to provide a data processing system for executing a time separated sequence of data processing operations in response to a single vector data processing instruction. An example of such a vector data processing system is the VFP (vector floating point) coprocessor designed by ARM Limited, Cambridge, England. Such vector coprocessors operate by using a single vector instruction to first select one set of registers upon which an operation is to be performed, performing that operation, selecting a next set of registers, performing the operation again and so forth. The VFP processor is provided with its own register data store for use with these manipulations. The register data store can either be divided into short registers each holding a short single precision floating point value or a smaller number of long registers each holding a long double precision value. Instructions allow separate operation on either single or double precision values.